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Customizable Embedded Processors: Design Technologies and by Paolo Ienne, Rainer Leupers

By Paolo Ienne, Rainer Leupers

Customizable processors were defined because the subsequent traditional step within the evolution of the microprocessor enterprise: a step within the lifetime of a brand new expertise the place most sensible functionality by myself isn't any longer adequate to assure marketplace good fortune. different elements turn into basic, resembling time to industry, comfort, strength potency, and simplicity of customization.This booklet is the 1st to discover comprehensively probably the most basic traits which emerged within the final decade: to regard processors now not as inflexible, fastened entities, which designers contain "as is" of their items; yet really, to construct sound methodologies to tailor-fit processors to the categorical wishes of such items. This e-book addresses the objective of keeping a really huge family members of processors, with a variety of good points, at a value resembling that of preserving a unmarried processor.

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Multiple access, coding, modulation, network structure) The cognitive approach will lead to a new paradigm in the cross-layer design of the communication networks. For example, on the physical layer, the increasing heterogeneity requires flexible coding, modulation, and multiplexing. Current state-of-the-art transmission systems, which Chapter 2 14 ■ Opportunities for Application-Specific Processors are designed for particular sources and channels, may fail in changing conditions. A new flexibility will be introduced: the traditional static design will be replaced by a cognitive approach with, for example, adaptive self-configuration of coding and modulation, taking the instantaneous statistics of the channel and the sources into account.

The outer receiver receives exactly one sample per symbol from the inner receiver. Its task is to retrieve the transmitted information by means of channel and source decoding. The inner receiver has the task of providing a “good” channel to the decoder. As can be seen from Fig. 5, two parallel signal paths exist in the inner receiver, namely, detection and parameter estimation path. Any digital receiver employs the principle of synchronized detection. This principle states that in the detection path, the channel parameters estimated from the noisy signal in the parameter estimation path are used as if they were the true values.

As a general rule, if the application comprises large C-programs such as in multimedia, the benefit of customization and scalability might be small. Since the processor is used by a large number of application programmers with differing priorities and preferences, optimization will be done by highly efficient and advanced compiler techniques, rather than architectural optimization. The application is not narrow enough to warrant highly specialized architectural features. For this class a domain-specific processor is probably the most economical solution.

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